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Recent content by lemart92

  1. L

    I2C Slave to Avalon MM Master

    Thanks for the detailed response ads-see. I'll go back and try to incorporate your suggestions.
  2. L

    I2C Slave to Avalon MM Master

    aruipksni - can you point me to the altera i2c slave that you used? I didn't find anything on their site. Thanks for your suggestion.
  3. L

    I2C Slave to Avalon MM Master

    Hi All - I'm fairly new to vhdl and I need to add an avalon memory mapped master to an I2C slave block. I've looked through a few pages but nothing really explains it. It looks like it's not that bad but I'm not really that good yet on writing the state machines.My code is pasted below: --...
  4. L

    VHDL Wrapper for Verilog

    Re: VHDL wrapper for Verilog Excellent! And thanks for the link.
  5. L

    VHDL Wrapper for Verilog

    All - I'm trying to instantiate this Verilog block (pasted below) into my top level VHDL. I've tried to create a wrapper but I'm not having much success. Can anyone help me out with how this is supposed to look with a VHDL wrapper around it? Thanks! `timescale 1 ps / 1 ps module top_hw (...
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    Creating EPCQ Block in Cyclone V

    All - I'm using the Cyclone V GT Development kit with the MAX V as the controller: https://www.altera.com/products/devkits/altera/kit-cyclone-v-gt.html#figure1 We have done the modifications to the MAX V and the Cyclone to get the active serial working. It doesn't work that way out of the...
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