Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I just want to know that FF works at posedge of clock and posedge occurs after every Clock period irrespective of duty cycle.So what does this duty cycle effect for a particular design?
and what are the factors on which it depends that how much duty cycle to use for a particular design...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.