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Recent content by lcf0451

  1. L

    Does Synopsys Certify support customer design boards?

    Hi, Anyone have used Synopsys Certify? Does it support boards designed by customers? Thanks
  2. L

    I want study ASICWhat is the future direction of asic design

    as the title.
  3. L

    Looking for IBM power processor block diagram

    IBM power processor you man G5?
  4. L

    lint tools for verilog

    cadence lec lint I think manay compiler and synthesis tools are integrated with lint toll.
  5. L

    help for Cadence® Encounter User Guide!

    give me you email, I will try to find it for you!
  6. L

    [help] how to set_dont_use in soc encounter?

    encounter sinkmaxtran What is soc encounter used for?
  7. L

    How to avoid glitch in a logic that selects CLK or CLK_invert?

    Re: glitch removal What is the relation of the select signal and the clock?
  8. L

    help: about netlist extraction.

    I want to simulate the design. Since the netlist extracted are only diode, not gate.
  9. L

    Help me do DDR simulation

    Re: DDR simulation I want to buy 200MHz DDR RAM for test of my RAM controller. Do you know where to buy it? Thanks
  10. L

    help: about netlist extraction.

    How to convert netlist extracted from layout to verilog format? Anyone has the perl program and can send it to me? Thanks
  11. L

    protocal T14 of ISO7816-3 of smartcard.

    iso7816-3 Anyone can tell me something about this? thanks
  12. L

    How to finish perfect verification?

    If you have perfect verification, then there are no verification.
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