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Recent content by lbdcdrc

  1. L

    Troubles with latched counter

    Sam, Are you only talking about the last entity (Which is called d_latch_12) or the whole design ? If it's only the last one, what's the proper way to implement the same function ? If not, how can I do ? I have the feeling that this design is working pretty fine... Thanks, Cédric
  2. L

    Troubles with latched counter

    ThisIsNotSam, I don't understand what the problem is ? My knowledge on FPGA is too short... Klaus, this solution is sooooo smart, because it's so easy ! Thanks a lot !!! FvM, I now understand ! I'll move all the signals to the clock edges ! I'm going to try all the modifications tomorrow...
  3. L

    Troubles with latched counter

    I didn't find how to edit my previous post, sorry for the double post ! Finally, it works, hope that the state of art are we me ! I also corrected a mistake that I made before. I don't use the RF profided by the synthetiseur as a clock, but as a clock enable. Here is the final diagram : And...
  4. L

    Troubles with latched counter

    Hey ! Many thanks for this code ! I simulate it, and, I think I'm now going to understand ! Here is the result of the simulation : So, the goal of this function is to synchronize the rising edge of RF_in with the rising edge of the main clock ? Is it true to say that I now have to...
  5. L

    Troubles with latched counter

    Hey, I kmow that you nerver suggested that, but you were talking about synchronizing the two signals, RF_in and clock... The only way that comes to me is using a PLL. I used your code, I now have a clean 100us second timer (on this example the timer was set on 5 for the simulation): But I...
  6. L

    Troubles with latched counter

    Oh, beginner mistake ! I didn't notice the 4001 divider ... Thanks for this code, it's going to be helpfull ! The reset name was choosen because this signal will reset the RF counter (the next stage)... Is PLL a good way to work on my troubles ? If yes, how to implement it ? You're very...
  7. L

    Troubles with latched counter

    My FPGA works with a 40 MHz oscillator, so I use the main clock wich is normaly 40,000 (10 ppm). So, if I understand well, I have to use a PLL based on my system clock (40 Mhz) and the unknow RF system (between 2 and 10 Mhz). Then I'll will have the two clocks synchronized ? Is this ok ? Many...
  8. L

    Troubles with latched counter

    Thanks for your answer ! I now understand the problem with the last D-latch. Please, excuse me for theses newbie questions, but i'm quite new on FPGA... I would like to make this design in the state of art, and it seems that you know the subject =) I understand that creating severals logicals...
  9. L

    Troubles with latched counter

    Hi all ! It's my first post here, so many thanks in advancy for any kind of help that you'll give =) I working on a project based on an FPGA. One of the goals is to check a frequency (wich is different and lower than the main clock). By surfing on this forum, I've decided to use 3 different...

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