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Thank you all for the great input. I learned a lot.
The takeaway is: DRAM cell lifespan is generally not a concern as the bottle neck of the device lifespan in normal operation mode.
And don't discuss philosophy here...
Hi KlausST, I know what you are saying, but considering the fact that read disturb problem indirectly contributes to erase necessity, read also affects the life span.
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Hi FvM, honestly, I don't believe anything will last forever except God... Even a capacitor has its...
I'm curious about the life span for a standard DRAM row or cell.
As we know current flash cells have their genetic life span in term of number of read/write access.
But how about DRAM cells? Is there a guaranteed life span(in term of read/write times) beyond which a given cell is doomed?
I can't...
Hi All
I need to add a 21-bit signal to a 32-bit signal, and it won't generate carry bit[33].
Since the clock is really fast, I'm trying to figure out how complex the ADDER logic might be, based on standard library from TSMC. For example, will the critical path have more than 21 NAND-like level...
Is example_prop1 totally equivalent to example_prop2 if being instantiated as "assert"?
property example_prop1;
@ (posedge clk)
(A |-> B ##1 C);
endproperty
property example_prop2;
@ (posedge clk)
(A && B |-> ##1 C);
endproperty
Thanks!
for example:
logic [7:0] vector_a;
logic bit_b;
logic bit_result;
assign vector_a = 8'h20;
assign bit_b = 1'b1;
assign bit_result = vector_a & bit_b;
I understand this is not a good coding style. But I'm just curious about the result.
Cadence NCSIM shows bit_result is...
if you are asking how Formal verification tools basically work, here is a general idea.
First of all, as dave_59 said, you have to "tell" the Formal tool your design SPEC, such as bus protocol, constraints, what is expected, or what is not expected, etc.
After you specify your design in a format...
If you are offended by my inadequate information, I apologize for it. I thought Vivado is just an evolved version of ISE.
I thank everyone sincerely for trying to help.
I agree with your 1ns => 1GHz limit claim. I was trying to say that it is usually the combinational clouds between flops that affect the fastest possible frequency a digital design can run at, not usually the hold time.
that's exactly the case. Great deduction
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Vivado has migrated ISE settings into new settings. In this case, logic_opt is included in opt_design, which is used in our current build...
The design in nature excludes the possibility of using bram, it is not a simple FIFO, the physical buffer will be divided into multiple logical FIFOs under different scenarios. I can only say so much.
I'll follow up with map optimization options.
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For optimization part, the...
I think barry's example is a bit extreme. I agree logically sunidrak's statement is not precise. but in general, hold time won't be longer than 1ns for current technology of 40n or smaller.
Also, it is usually the setup time as bottle neck of how fast a design can go. Synopsys document regards...
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