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Recent content by laughlatest

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    [SOLVED] What is the raised cosine filter and what is is used for?

    Re: What is the raised cosine filterr? They are used to transforming baseband digital signal into pulse waveform which is more appropriate for transmission through the channel. Therefore, they are also called as (the most important type of ) pulse-shaping filter. And sometimes they are called...
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    set_driving_cell for IO pad?

    Hi, all: I am confused about the usage of set_driving_cell. As you know, set_driving_cell takes cell name from library as its parameter. So in the bottom-up synthesis, for a sub-module synthesis, its input will be driven by another cell from the library, then set_driving_cell is used to define...
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    How to define clocks in my cases? S.O.S!!!

    iwpia50s, Thanks. My project is a netlist sign-off project, BE task is out-sourcing to 3rd-party design house, who provide us technology lib and also PLL IP etc. So I just wonder whether I can simplify my FE task as much as possible, and push the things to BE. Anyway, they are expert to deal...
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    How to define clocks in my cases? S.O.S!!!

    Hi, kulyapinav Thanks so much! Now I think I have got to understand your proposal correctly. Focusing on optimization of the path with PLL seems appropriate to me. The MUX cell(MUX2CK) comes from vendor's library, and is specific to clock switching, so I think I have no need to worry about it...
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    How to define clocks in my cases? S.O.S!!!

    Hi, Thanks a lot. I think that your proposal will work for me in case of clk_sel=1. I will just try it. One thing shall be clarified: In my design, PLL is used to double the clock frequency. When clk_sel=0, the CLK0 is a 64MHz clock and used as system clock directly, when clk_sel=1, the CLK0...
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    How to define clocks in my cases? S.O.S!!!

    Hi, kulyapinav: Thanks for your kindness. Surely, my chip has to provide reference sampling clock to external AD and DA. But the clock also comes from the MUX output, while not the input clock itself. I am wonder whether this fact simplify the problem to some extent. If I choose the MUX...
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    How to define clocks in my cases? S.O.S!!!

    Hi, all: The clocks in my design is: External input CLK0 can be either 32MHz or 64MHz, which is selected with clk_sel pin. CLK0 passes through a PLL to become 64MHz CLK1. Then with the help of clk_sel, either CLK1 or CLK0 is selected as the CLK2, which serves as the root clock of system. The...

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