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guess I'd need the help of you guys once more on this topic:
signal DQ : std_ulogic_vector( 7 downto 0);
-- memory simulation model
inst_name : entity_name
Port map (
E_b => CSN(0),
W_b => WEN,
G_b...
I realised now I wasn't very clear in my question. The question was related to type conversion, not port assotiations, sorry :cry:
The missing "," is not a syntax error, " . . . " is (it was on purpose).
yes, the conversion is neccessary due to type difference in port / signal.
LHS...
hello,
I just noticed this port map in the project I am working on:
custom_fifo
PORT map(
clk => clk,
. . .
std_logic_vector(q) => q
);
I have never seen such a thing. What's its purpose, how does it work, how is...
what does it say in the console? what are your configurations?
i am using Lattice Programmer https://www.latticesemi.com/Products/DesignSoftwareAndIP/ProgrammingAndConfigurationSw/Programmer.aspx
I marked the path as multicycle to close timing but the system is not stable anymore.
Anyway the FIFO must meet timing to work properly. I can only apply any relaxation if proper CDC takes care of this, like two-way handshake synchronisation
you will need to design a memory controller in VHDL that performs read / write operations. This is not a beginners project. Your FPGA vendor provides IP cores, you can also search on opencores.org if you can find an SRAM controller that works with your memory. I don't know of any, never worked...
I have a CDC from iCLK_SYS to sfXGMII_CLK_156. I am using a FIFO to buffer the data. The fifo is a black box model but appearently there is a counter r_gcount which is probably checking the watermarks or something. This is giving me a critical path as shown below:
Error: The following path...
exactly what i was looking for, thanks :thumbsup:. I use these PMI (or unimacros) quite frequently. I have them as code snippets and they appear 'as i type'. It takes me no less then 3 seconds to declare and instantiate them and they are parameterizable. No need to maintain it or keep several...
What I ment was a Parameterized Module Instantiation (PMI). It is basically the same thing without using IP core generator. You declare the component, and instantiate it.
- - - Updated - - -
This is an example PMI:
--!
--! fifo component
--!
component pmi_fifo is
generic (...
This is my 1st time using Vivado Design Suite. I need a FIFO. Where can I get the component declarations of Xilinx for parametric module instantiation?
thanks
yes, i ment the BIST. To run the BIST you have to load a bitfile to your FPGA, right?
That means there is most probably a LCD controller written in Verilog or VHDL that takes the control part. I expect your software to communicate with that controller, and the controller with the LCD...
Chances...
did you check the example designs from the manufacturer? some may use the LCD. Use this as a reference.
or else see if someone had been interfacing that LCD with a FPGA
Otherwise pick up the datasheet of your LCD and start coding...
- - - Updated - - -
the manufacturer of the LCD also has a...
that makes sense.
I tried your example and it worked for the 1st half of the sequence. This is because of the AND gates that make the sequence stuck at x"00".
I'm not sure what you ment to say with this.
I replaced the AND gates with XOR gates and it works perfectly :razz:
I still don't...
Yes, i am doing the "shift by one" style of lfsr with XOR gates.
To mirror the tap sequence in an n-bit LFSR I need to subtract the taps from n like so: [n, A, B, C] to [n, n − C, n − B, n − A].
And when the original LFSR is shifted to the right, the mirrored woul be shifted left, right?
The...
you should do a functional simulation to test your code.
... and a timing analysis. Are you sure your code can be implemented in an CPLD (see above)? Consider debouncing your buttons.
why are you setting your temporary signals assynchronously with your buttons?
elsif ( BTN0 = '0' or BTN1 =...
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