Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by lastguy

  1. L

    verilog generate with different module name inside the generated module

    many thanks! this looks good! I copied here for others; generate if (IF_WIDTH < 10) begin : if_name adder # (IF_WIDTH) u1 (a, b, sum_if); end else begin : else_name subtractor # (IF_WIDTH) u2 (a, b, sum_if); end endgenerate
  2. L

    verilog generate with different module name inside the generated module

    looks like VHDL can use if-else in generate but verilog can't.
  3. L

    verilog generate with different module name inside the generated module

    In Linux we can use ## to pull in a string and use it as a function name, now I want to do with module name in verilog. I want instantiating say four modules of mx(x=0~3), each instance uses a different module mmx to further instantiating mmy(y=0~1), so: mx m0() shall contain: mm0 mm00(); mm0...
See more

Part and Inventory Search

Back
Top