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Recent content by laodao01

  1. L

    how to switch multiple clocks inputs for the process?

    Your clk's frequency ? if less than 10M,you can use vhdl code to choose directly.
  2. L

    verilog synthesizeable operators

    c[31:0] = a[31:0] << b[4:0] means case(b) 5'h0 : c = a; 5'h1 : c = {a[30:0],1'b0}; 5'h2 : c = {a[29:0],2'b0}; . . . 5'h1f : c = {a[31],31'b0}; endcase
  3. L

    verilog synthesizeable operators

    it is synthesizeable. a << 3 works well. a << b is not recommended and will use too much resource. and you could use this : {a[5:0],3'b0} it equals to a<<3
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