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Recent content by laobian

  1. L

    Why use active-low in bus signal definition?

    Maybe for speed, but dont care about it in your design.
  2. L

    DC synthesis question ?

    synopsys design compiler set posedge set negedge Normally，one system just has only one RESET signal connect to the CLR or SET pin of DFF, not both of them. So, the result alway is the same.
  3. L

    Digital signal processing with VLSI

    yes
  4. L

    disadvantages of inferring latches.

    disadvantages of latches According to modern ASIC design guideline , there must be no any latchs in your design. Dont ask why!Except you use Latch as sequential cell.
  5. L

    Do I have to compile the VHDL sub-module in Modelsim?

    Anyone use ModelSim? If some errors occurs, you can compile again, then the error maybe doesnot exist.
  6. L

    Verilog Syntax Synthesis Question

    By the now, DC can only infer asyn reset or asyn set
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