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Recent content by Kyrillos Magdi

  1. K

    [SOLVED] Synthesis using Synopsys Design Compiler of Verilog Encrypted Source Code File (.vp file) that was generated using Synopsys VCS

    Yes, thanks a lot
  2. K

    [SOLVED] Synthesis using Synopsys Design Compiler of Verilog Encrypted Source Code File (.vp file) that was generated using Synopsys VCS

    I am trying to synthesize using Synopsys Design Compiler a .vp file that was encrypted using Synopsys VCS simulation tool, it is a part of a large project where there are multiple RTL Verilog files and this is the only one that is encrypted and is integrated to the whole system, it ran very well...
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