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Recent content by kyonglee

  1. K

    Clock gating cell constraints in design compiler

    I have clock gating cells from a standard cell library in my RTL design, and synthesize it using design compiler. Does design compiler automatically relates the input/output clock relationship of the clock gating cells? Or, do I manually specify clk constraints (e.g., create_generated_clock)...
  2. K

    CDL netlist tutorial?

    Hello, Is there any online cdl netlist format tutorial? I searched for one, but I couldn't find any. In particular, I don't understand what the parameters, 'r', 'par', 'sbar' and 'bp' mean in the following line. R3_2 P PADR1 opppcres W='4u' L='2.6u' r=249.937 par=1 sbar=1 bp=3 $SUB=AVSS...
  3. K

    [SOLVED] Clock gating in synopsys flow

    Hi ljxpjpjljx, I am using design compiler for synthesis and astro for p&r. Hi dianin, Thank you for your answer! By the way, can I ask what you mean by 'load enable'? Hi lostinxlation, Thank you for your answer! I want to specify the exact location for clock gating cells placement. I actually...
  4. K

    [SOLVED] Clock gating in synopsys flow

    Hello all, I have two instances in my top module. Say they are u1 and u2. I would like to insert clock gating cells for each of u1 and u2 and raised some questions. Could you answer my following questions? 1. I think clock gating cells can be inserted in either front-end (e.g., RTL level) or...
  5. K

    Astro multiple power domains

    Hi all, What is the flow for multiple power domains in Astro? I want two power domains and have two logic designs for each of the power domains. Vdd's for the power domains are same. I am just going to drive two power domains with different power sources. Thank you. -Kyong
  6. K

    Milkyway SRAM macro and astro drc

    Hello I am new to milkyway and astro. I designed a simple circuit using sram and some DFFs and got a lot of short drc in astro routing. I guess there's something wrong with my sram library generation flow so I have attached a cel view and fram view captured. (The cel view is generated from gds...
  7. K

    [SOLVED] Mapping unknown (X) to 0/1 in VCS

    Hi, I am using VCS for a gate level netlist simulation of my design. When my design doesn't meet timing constraints, i.e., setup time and hold time, VCS spits out X's. For my own purpose, I want to map these X's to 0/1's with equal probability and continue to simulate. Can I even do this in...
  8. K

    [SOLVED] Synthesize SRAM compiler output in verilog

    Thank you!! I didn't include .v file from my sram compiler but do include .db file. Design compiler consider my sram as a black box, so there is no sram synthesized in my gate level netlist, but timing report contains sram timing information. This is exactly what I want.
  9. K

    [SOLVED] Synthesize SRAM compiler output in verilog

    Hello, I am using artisan sram compiler and could get verilog view for my sram. I am trying to synthesize the sram with some glue logic using design compiler, but failed because the verilog code for sram is not synthesizable. I have tried to generate everything that I can generate from the sram...
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