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Recent content by kvk1806

  1. K

    Interview Question on Cmos

    CMOS based NAND gate is given with one input passed through transmission gate find the issues in circuit.
  2. K

    Cmos nand gate with one input through transmission gate

    CMOS based NAND gate is given with one input passed through transmission gate find the issues in circuit.
  3. K

    Comparator design in cadence

    i am using clocked comparaters and i want that the comparator should be operate in subthreshold i.e my supply vtg is 0.35v and while simulating i am not getting good freq i.e i am getting only in mega but i want that one should operate for high freq(ghz) so what are the options to increase freq...
  4. K

    Comparator design in cadence

    what is the initial region of operation for comparator when we use in 90nm in cadence?
  5. K

    analog IC design(double tail comparator)

    Hi, Have you tried double tail comparator,how much delay,power you got?
  6. K

    About transistors usage

    Thank you.For comparator design which type is better i mean nmos_1v or nmos_hvt(for low power,high speed apps).
  7. K

    About transistors usage

    what is the difference between nmoshvt and nmos1v in cadence (in terms of usage)
  8. K

    Tell me about double tail comparator design in 90nm technology

    I want to get output of 400mv at outputs N,P when we gave input at N,P=400mv. Can anybody tell me the aspect ratios values for each transistors.I gave power supply of 800mv thats why i put 400mv each dc volatges in either side i.e for positive and negative inputs.
  9. K

    Comparator

    hello, I want to design a double tail comparator to reduce offset for better speed and resolution of ADC's and also i am interested in reducing kickback noise for that so can any one tell me about latest techniques to reduce kickback noise.
  10. K

    project

    Can any body tell me about best noise reduction techniques for better offset in comparator?
  11. K

    Suggestions

    Can anybody suggest me about this project (Invasive Process compensation Technique for Sub-Micron CMOS Amplifiers).Please give me suggestions on how to approach on this project,scope for new techniques and also designs
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