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Recent content by kuseraj

  1. K

    How to simulate Core Generated Model of Xilinx....?

    hai, just give the inputs from test bench an simulate it with regs, kr
  2. K

    who have these two document

    hai, lot of materials are available in google
  3. K

    Gigabit Ethernet core need

    hai, Evaluation version is available in xilinx website.
  4. K

    Learning testcases in Verilog

    Re: TESTCASES IN VERILOG first u learn test benches , according to ur design u write corner test cases
  5. K

    Why there is no transition with autoprecharge in DDR SDRAM?

    Re: DDR SDRAM auto precharge is reqired to close the particular bank
  6. K

    problem with simulation in Modelsim in UNIX environment

    Hai,i f i use the below code same error is displaying. what to do?
  7. K

    problem with simulation in Modelsim in UNIX environment

    when i simulate the ROM module the following error is coming. pls help me regarding this Exited with exit code 12. this refers to problem during load or elobaration vsim rom.v # ** Error: (vsim-19) Failed to access library 'rom' at "rom". # No such file or directory. (errno = ENOENT) #...
  8. K

    Problem with simulation in Modelsim SE Plus 5.7e

    error: (vsim-19) when i simulate ROM module in unix environment the following error is coming. # vsim rom.v # ** Error: (vsim-19) Failed to access library 'rom' at "rom". # No such file or directory. (errno = ENOENT) # Error loading design Error loading design Sender: LSF System...
  9. K

    BIP(Bit Interleaved Parity)- VHDL Code

    bit interleaved parity-8 Hello all, I want to implement BIP-8 for SONET/SDH( Bit Interleaved Parity) for FPGA. Anybody is having VHDL code, please inform. with regards, rajendra
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