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non linearity sigma delta
I have designed a sigma-delta ADC (OSR=2048, BW=50Hz, fs=200kHz)
by switched-capacitor.
I run FFT in Hspice, and get the very poor linearity behavior,
Can anyone suggest for me?
thank you!
sigma delta adc design procedure
Hi analoggg:
Thanks for your reply!
Dose the dither circuit be difficult to implement?
Do you have dither circuit paper or data?
If I use high-order sigma-delta , is there no idle tone in spectrum?
Thank you very much!
Thank you,santom!
Can I ask a question?
The Vin < 0.25*Vref
If I design a 16-bit ADC, I only have output value 65535*0.25 (0.25*Vref)=16383?
so I have output value only form 0~16383? Is it right?
Thank you!
Thank you very much!arunkumar446!
Can I ask another question?
If I scale the factor, the Vin doesn't go to full scale value??
(i.e. Vin < Vref ? If Vin can not equal Vref?)
Thank you very much!
delta sigma adc type 4
Hi analoggg:
What method can I prevent the idle tone(limit cycles) with DC input??
And what is the mean "-> above 1V dc modulator wont produce any limit cycles."??
Is the input value above 1V??
Thank you!
What happen if input DC value to sigma-delta ADC?
Can I use DC value input to sigma-delta ADC?
And what consideration to design the sigma-delta ADC?
Thank you!
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