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Recent content by kun

K
Problems with 8 bit DDS as it stops "half way"

Re: DDS Help err i try already but errr offset everything just change the size of the wave but still i see - and + on my wave
- kun
- Post #26
- Dec 13, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

Re: DDS Help see this
- kun
- Post #24
- Dec 13, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

dds change offset err we know that The vertical scale on the "sine" signal is from -128 to +127: is there a way that i change shift the whole sine signal like 128 to 255
- kun
- Post #22
- Dec 12, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

xilinx dds testbench err but i like to know if i can move 128 to -91 to both postive like 128 to 91
- kun
- Post #20
- Dec 12, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

coregen dds quadrature problem i was ask to shift the whole wave above the zero . can that be done ??
- kun
- Post #18
- Dec 7, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

xilinx dds sclr thanks for the help ^^ im not very good in VHDL what sclr you think is the best ? uut: dds PORT MAP( sclr=>sclr, clk=>clk, SINE=>SINE ); sclr <= '1','0' after 1 ns; tb : PROCESS BEGIN clk <=...
- kun
- Post #16
- Dec 7, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

dds compiler ver 3.0 + ise 'sclr' pulse is too short ? It isn't providing good setup time before the clock. how do you lengthened the pulse? err so you mean under my DDS setting . i got to set the DDS Clock Rate lower ? but i set it 300 MHZ or 250 is still show the same thing =( is there...
- kun
- Post #14
- Dec 7, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

dds compiler v2.0 simulation modelsim err nothing after 100ns is all the red line errr what you see. is all i have don know why when i run 9 or 10 bit nothing wrong you can go all the way to 100ns but . when i try on 8bit . error . anyone know how to solve
- kun
- Post #12
- Dec 6, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

quadrature oscillator using dds in xilinx err how to check whether the vertical scale on the "sine" signal is from -128 to +127 . and is there a way you can shift the whole "sine" singal to upper the Zero like moving the whole sine above zero
- kun
- Post #10
- Dec 6, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

modelsim dds this is what i got
- kun
- Post #9
- Dec 6, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

dds help MOdelSim XE III/Starter 6.1e - Custom Xilinx i using Direct Digital Synthesizer 5.0 this is what i get sad :cry:
- kun
- Post #8
- Dec 6, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

dds compiler err i got my 8 bit signal half way . it stop and all the way become red line . there's my test banch ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS COMPONENT dds PORT( clk : IN STD_LOGIC...
- kun
- Post #6
- Dec 5, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

dds modelsim err i got a wave and but it only showing iit half way
- kun
- Post #5
- Dec 4, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
Problems with 8 bit DDS as it stops "half way"

dds compiler example xilinx Xilinx okies i got my 8bit but i don know what happen it only show me the wave half way . from 0000 to 0101001 the rest nothing .... i don know why . any one help~~ please
- kun
- Post #3
- Dec 4, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
K
How to set the core_gen signal ?

Re: core_gen jason where are you i need to ask you about DDS help~~~ reply me asps tmr afternoon i need to test hope you see this message drop me email ( hey_56@hotmail.com ) how to make the DDS 8bit 120MHZ 10bit cannot test need 8bit
- kun
- Post #18
- Dec 3, 2007
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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Recent content by kun

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

Problems with 8 bit DDS as it stops "half way"

How to set the core_gen signal ?

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