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Recent content by kumard35b

  1. K

    [General] Technology Process node

    Hi, I would like to know the technology process node of JN5168 it is a micro-controller used in controlling home appliances. Regards Kumar
  2. K

    Difference between HV CMOS and BCDMOS

    DMOS is Double Diffused Metal oxide Semiconductor. The cross section of a VDMOS (see figure 1) shows the "verticality" of the device: It can be seen that the source electrode is placed over the drain, resulting in a current mainly vertical when the transistor is in the on-state. The "diffusion"...
  3. K

    LDO structure question

    ka nang leung site:edaboard.com the internal compensation is done inside the opamp. The capacitor is made of mos transistor so that externally you don't need to connect a capacitor for loop compensation,however you need to have full stable operation a small amount of capacitor to be connected...
  4. K

    Beginner in analog circuit design

    millman is +good advanced rapidshare you can view some online lectures and get the design concepts https://freescienceonline.blogspot.com/2006/06/engineering-video-lectures.html
  5. K

    help for good understanding of analog concepts

    what takes to be a good analog design you go listen to some online lectures of analog design https://freescienceonline.blogspot.com/2006/06/engineering-video-lectures.html
  6. K

    psrr issues in ldo design

    you can connect a bypass capacitor at the output of your bandgap voltage externally to reduce psrr caused by bandgap circuitry
  7. K

    How to modify the netlist extracted by cadence cdl?

    cdl cadence once u extract the netlist you can go to the file whether it has extracted and open it in vi mode or in nedit and edit and save
  8. K

    Need some interview question about LDO and DC-DC converter

    sample ldo interview questions some more to add people may ask about the settling time and accuracy of LDO
  9. K

    Problem about POR(power-on reset)

    you can design a comparator to monitor the voltages
  10. K

    what is the meaning of ESR of Cout in a LDO? thanks

    ESR adds zero while doing compensation
  11. K

    what is Monte Carlo in circuit design?

    Normally now a days monte carlo analysis is done agressively to find the process and mismatch parameters ie to compare the simulation results and silicon results.
  12. K

    Monte Carlo Analysis in Cadence

    you need to set the coefficients as default parameters if you change anything then the simulation results and the silicon results will differ.
  13. K

    Looking for friends who study DC-DC boost covernter

    Here is the answer for your questions 1.what is the quiescent current of a boost converter? how to understand that condition:no switching? Ans: The quiescent current is the current which is drawn from the supply when the DC DC converter is in the idle mode ie no switching activity .You may...
  14. K

    Can I use the minimum size of a transistor?

    you can use minimum sized device..but sometimes it may fail due to short channel effects..for this you need to do a spice or spectre simulation by making the input current or voltage whichever is applicable for your circuit and do DC simulation ie the circuit should operate in idle condition...
  15. K

    analog layout materials for beginners

    You can refer Book :Art of Analog layout by Hastings Some useful tips for comparator layout are Common centroid techniques,proper matching of input pair.
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