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Recent content by kumaranurag21

  1. K

    why set_driving_cell is required for clk port

    Hi When clock port is primary port of a block Why do define appropriate driving cell with high drive strength? Regards Anurag
  2. K

    Why 1x fillers are not available in 28 nm and below technologies

    Hi Folks I had one doubt Why 1x fillers are not available in 28 nm and below technologies....plz clarify ??
  3. K

    My Psynopt is failing....plz suggest possibe reasons

    Hi all My psynopt is failing....I am getting the following Error PSYN-450. I looked into the solvnet which says "You get this error because the placement utilization is extremely high. The utilization reported here may be different than the utilization reported in other parts of the tool due to...
  4. K

    Which is more dangerous for my design - Crosstalk Noise or Crosstalk Delay

    Which is more dangerous for my design - Crosstalk Noise or Crosstalk Delay ??
  5. K

    How are always on buffers characterized in .lib

    How are always on buffers characterized in .lib ??
  6. K

    Why data tran violation is present?

    Re: Timing is clean yet data tran violation is there Thank you very much for the answer . One more query regarding clock tran violation.....do we always need to fix clock tran violation and if we not then what will be its impact on the design ??
  7. K

    Why data tran violation is present?

    Hi My timing is clean for my block but I still have data transition violation.Is it okay to say my design is closed or I need to fix all data tran violation?
  8. K

    Floorplan estimation

    Thanx for the reply One more thing, regarding floorplan....what is the funda of using nand equivalent for estimation of size of the cell for estimating the shape and size of my floorplan ??
  9. K

    Floorplan estimation

    Hi everyone Lets say I have a netlist consisting of 200k gates and I have to estimate die area and floorplan and deliver the DEF to placement team. How do I go about it ?
  10. K

    EFP violation in Physical Verifiaction stage

    Can anyone tell me what is EFP violations in Physical Verification stage? This violation is ainly seen in 28nm technology node

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