Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by kudo1017

  1. K

    How to build reasonable signal sequence

    now I get your point, thank you.
  2. K

    How to build reasonable signal sequence

    Thank you so much for your penning design suggestion, I will give a go and feedback about it here. But still I don't think this style is alleged 'standard FSM style', cause what I learnt in school lectures is to include all state-shifting-conditions into the FSM, the most significant difference...
  3. K

    How to build reasonable signal sequence

    As a newbie in this industry, im now very eager to learn about proficient skills of signal sequence building. As I was checking about those codes inherented in the database, I find those styles are so different from what I've learnt in the universities. I wonder if there's any book or well-known...
  4. K

    regarding floorplanning

    What a shame...I'm right a SOC student...and I even don't know that's the alternative name of IPs or cores, thanks for your nice answer!
  5. K

    regarding floorplanning

    What is a macro?I m a fresher for floorplanning....actually just know it in last course lab..
  6. K

    How to measure DELAYS for tris-gates?

    Hi there, I'm a student and now writting a .sp file(for SPICE simulation) to test the delays of a trisbuffer cell in the cell library designed by myself. Now Im confused by what is the proper way to measure the delays for its 'Enable' signal. Cause for each other cells, I normally just write...

Part and Inventory Search

Back
Top