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Oh yeah... I don't remember with Xilinx ISE 4.2...but i know that witht XIlinx ISE 5.1, when you try to program a bit file via JTAG that has been generated to start with the CCLK set as it's starting clock, the software will warn you about it (and i think it ask you to modify the bit file to use...
Re: xilinx bit files
I know for sure that if you connect a JTAG port and try to download a BIT file with it, it will override any of the programming mode selected by the mode pin.
For the difference between the two BIT files....There's a difference between the two of them...and I think it's...
Also, you need to decide if you want to program FPGA in Verilog or in VHDL. I prefer usign VHDL...but i guess it's a matter of taste.
There a lot of good ebook about VHDL (and also verilog) in the ebook section of the Elektroda forum so make sure you stop there.
ktuluboy
Regarding the software you could use to design FPGA.
1) A good way to start if you work with xilinx software would be to download their free software they call the ISE WEBPack. You will be able to synthesize almost every X*Ilinx FPGA with less than 300kgates.
2) If you want to do some...
xilinx xc3042 file
Hi,
Could somebody tell me where i could find (or download) an old version of Foundation that support the XC3000 series?
THanks,
ktuluboy
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