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Re: Why simulation results differ between quartus & mode
Well i think i found it.
There is a way to simulate in modelsim at a gate level. All i had to do is to properly set the EDA Tool in quartus.
In this way quartus copies all the necessary libraries which contain the device properties to...
Hi everybody!
Could someone please explain to me why a simulation that is correct in altera quartus isn't in modelsim?
I have quartus 7.2 web ed. and modelsim 6.2b (NOT altera version).
I ran a simulation based on a waveform file i created in quartus and then i exported the report to a verilog...
State machine problem in qu(at)rtus - Please help
Thanks a lot FvM!!
Finding this by myself would be quite impossible, considering the hugeness of the quartus handbook...!
:)
State machine problem in qu(at)rtus - Please help
Thanks a lot!
I think i understand how it works although it seems a little strange.
So in the end, is this going to work properly or am i going to have to change the first state to "001" instead of "000"??
The only thing that bothers my is...
Hi everybody!
I have a verilog design compiled in Altera's quartus 7.2 web edition.
The design has the following state machine (the whole file is attached also) :
...
reg [2:0] idest_addr;
...
case (idest_addr)
3'b000 : r_out=data_in;
3'b001 : e_out=data_in;
3'b010 ...
Hi there!
I have a question regarding verilog.
I have a very simple shift register like code like this :
module eleos_sub(NOCclk,in2,full3);
input NOCclk,in2;
output full3;
reg [7:0] mem=8'b0;
reg full3reg;
assign full3=full3reg;
always @ (posedge NOCclk)
begin
if (mem[7]!=1'b1)
begin...
You are totally true. Specs are incomplete. Sorry about that but i am a verilog noob. :)
The only things i can add are:
- inputs are buffered. In fact input data come from shift registers.
- There is a master clock and all operations(not sure about this one) occur at the posedge of this clock...
Hi everyone!
I am stuck. I need some help with a mux...
:)
I want to design a mux that has the following specs.
- 5 inputs (one bit wide ) & one ouptut (one bit wide)
- All input channels have an enable signal. (Just to declare that the input is ready to transmit)
- At any given time the output...
for loop in verilog code
OK so understand that only during simulation this is going to be executed sequentially unless i use a nonblocking assignment.
correcting my code so that overwriting mem[7] makes sense... :)
begin
output<=mem[0];
for(i=0;i<7;i=i+1)
begin
mem[i]<=mem[i+1]...
verilog for loop example
I have a similar question about for loops.
Let's say i write:
begin
for(i=0;i<7;i=i+1)
begin
mem[i+1]=mem[i];
end
mem[7]=0;
end
is this synthesizable??
Is it certain that all the statements are going to be executed sequentialy and NOT concurrently??
Is it FPGA...
Hello everyone!
I have a question for a module design in verilog.
I have two modules as this :
module top(...IN,....,OUT);
...
reg [7:0] in_register;
reg [7:0] out_register;
wire [7:0] wire_in;
wire [7:0] wire_out;
assign wire_in=in_register;
...
bottom instance1(..... wire_in, ...
verilog generate example
So now if i want to drive all the shift registers' outputs to the main output also like this :
Is there anyway i can do it?
Depending on some condition the output will be fed by one of the shift registers' outputs.
Thanks in advance.
generate in verilog
It works fine i tested it!
I added something like those two lines
assign sdata[0]=SI;
assign SO=sdata[size+1];
to assign the input to the first wire and the last wire to the output & it worked.
Thanks again!
generate verilog
Thanks a lot FvM!!!
That's exactly what i was trying to do but wasn't sure of how to declare the wires...
So the line:
wire sdata[SIZE+1:0];
does not declare a bus of wires right?
just a number of wires that can be placed wherever needed and be referenced by their index...
verilog generate
Hi everybody!
I have the following code that works as a shift register :
module sreg (C, SI, SO);
input C,SI;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp = tmp << 1;
tmp[0] = SI;
end
assign SO = tmp[7];
endmodule
And I want to create multiple instances of the...
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