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Hi Din :
ECOs are generally iterative in nature. As said in the previous post one need to look into the timing report and see whether to size the cell up or insert buffer or clone all depends on the situation. Generally its always better to try out with the required changes...
Hi Vikram :
1. when slew is slow as u said there would a high current flowing from VDD to VSS for a long time causing an increase in power as well as it would slow down you cell and increase the delay of your cell as delay is a function of both input slew and output load
2. if the slew is...
+timing reports .rpt
Hi Din:
1. The transition at the input pin would have worsened since by upsizing the cell the input cap increases which could load the previous cell (low drive) and would caused a timing degradation.
2. we need to see the i/p transition and output load. i/p tran could be...
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