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Recent content by ksahil

  1. K

    Question about Synopsys dft OCC flow

    Hello, can anyone please provide a good document for studying OCC Thanks and Regards
  2. K

    Reset Recovery and Removal Time

    hi... i have one doubt that even if we synchronize the reset, then wont there be any problem when that synchronized reset is going in design and reseting a flop in which clock is skewed w.r.t clock used in reset synchronizer.... thanks
  3. K

    synchronous reset or asynchronous reset?

    hi... i have one doubt that even if we synchronize the reset, then wont there be any problem when that synchronized reset is going in design and reseting a flop in which clock is skewed w.r.t clock used in reset synchronizer.... thanks
  4. K

    reset synchronizer to avoid metastability of async reset

    hi... i have one doubt that even if we synchronize the reset, then wont there be any problem when that synchronized reset is going in design and reseting a flop in which clock is skewed w.r.t clock used in reset synchronizer.... thanks
  5. K

    Why are reset synchronizers used ?

    hi... i have one doubt that even if we synchronize the reset, then wont there be any problem when that synchronized reset is going in design and reseting a flop in which clock is skewed w.r.t clock used in reset synchronizer.... thanks
  6. K

    synopsys design compilerdc_synthesis

    hi, i am a new user to synopsys design compiler... please tell me how would i check connectivity of different ports after synthesis. for example if i need to know whether ATP pin has been brought on top or not..or if i need to know its complete connectivity in design please help
  7. K

    What's the difference between the target library to the link

    hi.... why ram or macro library is not included in target library....??
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