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calibre lvs error
Usually LVS operation starts from the node correspondance points.. you have not placed the pin layer.. i think you have just put the label on metal.. in virtuoso layout designer there is tab called create -> pin .. type the pin name, assign it as in or out, with suitable pin...
what is salicide
Salicide is a layer used to increase the sheet resistance of poly, source/drain diffusions.. this layer will be put after the source/drain diffusions and before metal contact is done. This is layer which is put above the source/drain diffusions.. so you can connect the...
Some of the care that should be taken while designing PCB are as follows -
1. Use high frequency decoupling capacitor and place it close to the IC between Vdd and Gnd. Use tantalum capacitor for decoupling. Use capacitance 0.1 F for frequency less than 5 MHz and 0.01 F for above 5 MHz...
i agree with krashkeoloha.. also in lateral pnp the carriers move along the surface from the emitter to reach collector surrounding it.. due to discontinuities and surface effects some of the charges gets combined.. so the gain will be less.. but in vertical npn due to NBL and deep n+ regions...
Anand Srinivasan is right.. beta in bjt depends on the area of the emitter.. more the size more carriers are injected into collector. The BJT process optimizes the npn transistor at the cost of pnp. so the gain of npn will be around 100-150 while that of pnp will be around 30-50. For emitter...
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