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Recent content by krishvamsi

  1. K

    Fixed point multiplication in Verilog

    yes exactly . can u tell me the logic u used ? i'll be using it in verilog - - - Updated - - - can u please elaborate this ? i have 5.1 and -3.15 . from where u got -50 and 82 ?
  2. K

    Fixed point multiplication in Verilog

    the intended result should be in 16 bit signed fixed-point format which should be equivalent to that actual product i.e -16.065
  3. K

    Fixed point multiplication in Verilog

    i have two 8 bit signed numbers which i'd represented in fixed-point . one is -3.15 = 1100.1110 , other number is 5.1 = 0101.0010 . now i want to obtain the product of these two numbers in verilog. Manually i got the product as 0100000111111100 which is not equal to -16.065. how should i make it...
  4. K

    [moved] verilog code of a neural network

    Re: verilog code of a neural network i'm very confused . There are so many MAC operations involved . how to make them run in parallel . can u just tell me step by step ? input has 4 neurons.
  5. K

    [moved] verilog code of a neural network

    Re: verilog code of a neural network yes, ofcourse.
  6. K

    [moved] verilog code of a neural network

    i have a trained neural network with 4 input neurons, 7 hidden neurons and 3 output neurons , 49 weights and 10 biases . Now i have to implement it on an FPGA . How do i start verilog code for this ?
  7. K

    neuron modelling using MAC unit

    Yes . is there any possible way ?
  8. K

    neuron modelling using MAC unit

    I have finished designing a 16 bit MAC unit . now how should i implement a simple feed-forward neural network on FPGA using the MAC unit ?
  9. K

    lookup table implementation in verilog

    you didnt get my question. there is nothing wrong in the design . by using case statements i only assigned outputs for corresponding inputs as 0.011,0.087,-0.045,-0.415 . but in the simulation all 0's are coming . do u know how to assign the above numbers in verilog ? please help me out . i got...
  10. K

    lookup table implementation in verilog

    hello i used combinational logic for implementing LUT by using case statements . whatever values i gave are not coming exactly in the simulation. only integer part is coming and fractional part is not comimng . for ex: 5.734 . my simulation is showing only 5 . how do i get the exact values ?
  11. K

    lookup table implementation in verilog

    Floating point representation in Verilog how to represent these numbers in verilog? 0.011,0.087,-0.045,-0.415
  12. K

    lookup table implementation in verilog

    Then how can I store it ? Will you please tell me any other way
  13. K

    lookup table implementation in verilog

    here i need to partition the lookup table based on sd0 which acts as enable . latches are used to freeze the address of lookup tables . At a time only 1 lookup table will be active . i have to connect 4 such LUT's to the latches . how to store these values in a memory in verilog...
  14. K

    lookup table implementation in verilog

    This is the figure i was talking about . - - - Updated - - - i'm doing a project on design of a low power logarithmic arithmetic unit . As you know logarithmic addition is complicated which is given by logb(x+y)=logbx+logb(1+b^-(logbx-logby)) . so a lookup table is required for computing the...
  15. K

    lookup table implementation in verilog

    how to store the following values in a lookup table (2 dimensional memory) which is connected at the output of 8 bit latch in verilog ?? values to be stored are 0.011,0.087,-0.045,-0.415
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