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Hi Rahul,
Hold time does not depend on frequency because, this check is done at the same edges. where as the setup check is done after one clock cycle
hold check is done at the same edge to make sure that the data using at that cycle is the one latest, not the old data
Sasi
Hi Rahul,
At present technology, for example consider same cell is utilised twice/thrice in your design. then the behaviour of this cell will not be same. so we check the timing for the complete design use different corners (PVTs). There might be some paths which would be clean in timing wrto...
Hi All,
i am having PG ports (VDD and VSS) in my Synthesis netlist; i see having these in given RTL;
should i need to remove them or not.what happens if i forward to next steps using the same netlist?
how these PG ports effect the total flow if present in Synthesis netlist...
Please help me...
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