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I have an entity for clock_gating in my design, which should be synthesized as a specific clock gating cell in one of the libraries that I have loaded into Genus.
However, Genus doesn't seem to recognize this cell to be used, and instead synthesizes my clock gating entity to separate cells...
I'm currently writing a synthesis and PNR flow in Cadence Genus. I want as much as possible to be automatic.
Hence I'm trying to figure out how what command to use in order to return a list of instance names that mach a string.
From the documentation, there are several commands that I feel could...
There used to be a free student version of modelsim, however I'm not sure if it's still available. Vivado is my goto software for early RTL simulations.
I've heard good things about Yosis for synthesis, but not used it myself.
Besides the main clock, I had a couple of external clock sources to two peripherals, SPI and JTAG. I didn't define those as clock sources during synthesis hence neither were affected by the clock tree and thus not fulfilling the needed hold and setup slack
When reading the Pulpino datsheet, I noticed that the authors had made a graphical logotype on the layout using cell placement.
Is there an neat way to do this in SoC encounter during place and route? My thinking is that I can calculate the specific coordinates to describe my logotype and then...
Looking at the wave where the first hold time violation that occurs, I can see that the data D arrives at the same time as the clock CP in data_int_reg[8]. How can this be since the WNS hold in the PNR result is 0.4ns?
I have tried simulating with and without the SDF-file, and the result is the...
I'm using Pulpino from github. I've changed the RAM and removed some of the peripherals.
I've passed both RTL and post-synthesis simulations with results as expected.
In the P&R after nano route, when i run report_timing -early and report_timing -late both the hold and the setup slack is 0...
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