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Hi Folks,
Can any one explain how tap cell is used to prevent latchup effect.
I know tap cell is used to connect n and p substrate to Vss and vdd respectively. In google I found one more definition tap cell is reduce resistance between vdd and vss.
Thanks in advance,
kpsr
Thank you for your answer.
I hope there are two types of fillers
1. Filler cell -> which gives N-well and P-well continuity
2. Metal filler -> which provides proper metal density.
Please correct me if any thing wrong.
Hello Guys,
Recently I studied some where regarding filler cell like this can any one please explain the following statement in detail.
Filler cells also provide decoupling capacitance to complete the power connections in the standard cell rows and extend N-well and P-well regions...
Hi,
Lets think you didn't gave .lib in ASIC flow. How to know functionality of cell or cell delays or transition time or internal power for each cell.
.lib contains cell delays , functionality and power information.
In fab they will run different spice simulations and prepare .lib files.
Hi Folks,
We are specifying some x distance (50u) between tap cells.
How they are specifying this distances. On what bases they they are specifying a particular value.
Please replay this as soon as possible
Thanks in advance
kpsr
Hi Folks,
I need small help regarding virtual clock and real clock
Question ::
If I define two different clock periods for virtual clock and real clock what are effects we can see in design
Ex :: virtual clock is vclk 1000ps
Real clock is 1500ps
What type of effects we...
Hi vasaroopak,
For ever signal having transition period we will calculate cell delay based on input transition and output load.
we will put some transition limit for every pin if transition of signal is greater than our limit then we report the signal as a violated path.
Hi folks,
I am seeing transition violation on output pin of the cell even though input pin transition and output load is fine.
Input pin transition is good output pin load is small. I am seeing transition violation on output pin of the cell. I am not getting the reason for this issue...
HI Prestonee,
Thank you for your response, Actually this is case a i got in my design In physical design STA how the designer designed I don't know but what I am expecting is not getting, How to overcome this situation.
Actual situation is at 3ns clock is rising edge at the same edge...
Hi folks,
For a flop both set and reset pins are one then the flop goes to unknow state how to over come this situations in industry.
What I know is we can add a delay for any of the pin (set or reset). But on what bases (or) How much delay can I add.
Please let me know as soon as...
Hi folks,
Can any one please tell me the exact difference between multi power domain and multi voltage domain. If possible explain with example
Regards
kpsr
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