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Hi
I am trying to run PEX using calibre. I am able to generate .spef(PEX file) by using gds as an input file.
If I try to run PEX using DEF file it is generating an empty .spef file without any parasitic extraction.
and I got the following warning :
no nets in pdb
can anyone tell me where...
In my chip layout I got a DRC error stating LATCH UP; but after inserting the filler cells I didn't get a DRC error due to LATCH UP;
So please tell me how filler cells prevents LATCH UP (as it is an empty cell without any function)
In SRAM or DRAM sense amplifier operates in linear or saturation region
I have this doubt in digital circuits we operate in triode region but please tell me whether the sense amplifier alone operates in saturation region in SRAM or DRAM deign.
why manual routing is used in case of memory designs like DRAM and SRAM ?? why not automatic routing.
I have designed an ordinary 16 bit ALU where we performed Automatic Routing using Encounter. But while designing DRAM or SRAM we were told to do manual routing. Please tell me whether automatic...
I have 3 questions:
In a satellite communication why the up-link and down-link frequency are different
Why rain fade occurs at higher frequencies not at lower frequencies
Is frequency and power directly proportional
Thanks for the reply..
A compiler used to convert high level language to assembly language. An assembler used to convert assembly language to machine language(executable format)
Then what is an object code?? or machine language and object code same
Why in an 32 bit length instruction program counter incremented by 4?
for 16 bit and 64 bit by how much a counter should be increased? reason?
thanks a lot for your reply
Hi I have designed a 8-bit counter using verilog.
I simulated it using modelsim. counter is performing it's function correctly till the total event at the output reaches 127 (i.e after counting 127 clock cycles)
but after 127 I am getting a value of -128, then -127,126,-125 and so on for each...
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