Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
rf esd
In RF receiver input ESD design, I'm afraid the noise of power supplier of the IO BUFF crosstalk into the RF input. How can I solve the problem?
Thanks,
divider phase noise simulation spectrerf
Question:
To do normal divider's phase noise simulate with SpectreRF(PSS + Pnoise). The Sweeptype "relative" or "absolute" have great effect to the phase noise simulation result, why?
If sweeptype set to "relative", the phase noise is about...
Question:
To do normal divider's phase noise simulate with SpectreRF(PSS + Pnoise). The Sweeptype "relative" or "absolute" have great effect to the phase noise simulation result, why?
If sweeptype set to "relative", the phase noise is about 140dBc/Hz@100KHz, but if sweeptype set to...
Question:
1. to design one 2.4G frequency synthesizer for Mixer, one proposal is to design 2.4G frequency synthesizer with 2.4GHz LC VCO, directly ouput for Mixer. The other proposal is to design one 4.8G frequency synthesizer with 4.8GHz LC VCO, through one CML divider, generate 2.4GHz...
pll divider
Question:
I want to design one 900MHz, 0.18um PLL. I found the feedback divider can be designed with normal digital D flip-flop. So it's better to design the divider with analog(such as CML) flip_flop, or normal digital D flip_flop? Which one is better?
Thanks,
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
