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Thanks for the tips. I'll try to get used to and implement them to the assignment! Tomorrow I'll have the opportunity to test the code on a FPGA and see the end result.
Hello!
Don't look at the scheme as it has to have a meaning! It's an assignment to practice what I've learned about verilog for the past week. The code as it is, is working and the test bench is showing the results that I expect. I'm looking for optimization suggestions. Any help will be...
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