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I am using a STM32F4 FSMC to address external 16-bit SRAM on a custom board. Everything is OK.
I want to connect an external FPGA and I'm not so clear about the actual addressing.
Please correct me if I'm being stupid, the MCU is 32bit, but the internal AHB address bus is bytewise. The...
To demodulate AM, I use the formula am = sqrt(I*I + Q*Q)
I am mixing an AM IF signal to baseband, i.e. carrier plus 2 sidebands. My test signal is modulated at 800Hz.
When I look at the demodulation, it looks OK when I mix perfectly to 0Hz, but as the transmitted signal moves up or down...
I have a question about under-sampling.
I need to look at a 1MHz band of RF.
What approach would you take?
1) direct down conversion to baseband using an analogue IQ Mixer.
2) use a standard IF of 10.7MHz and over sample at 42.8MHz. Mix this down to baseband using a dual NCO / FIR filter...
Thanks, I shall try it.
My code did work but Quartus only gave a maximum clock of 30MHz which was too slow.
I altered the code for parrallel operation but Quartus only gave a maximum clock of 16MHz for this!
I have bought Quartus subscription to use the in built filters, but these use the...
This is something I've started,
does this look ok?
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_signed.all;
entity AD7492_CTRL is port
(
CLK : in std_logic;
RST : in std_logic;
ast_SOURCE_SOP : out...
I want to use an Altera FIR mega function. To connect to it I have to use the Avalon Streaming Interface.
I want to connect an ADC, filter the signal and store the result in SDRAM.
Has anyone got a VHDL template or example of the streaming interfcae I can use to get me started.
I use Altium...
I am trying to demodulate a phase shift signal.
The (mixed down) carrier varies from 25KHz to 34KHz. There are actually 4 channels of 3KHz. The signal is a burst of 150ms carrier followed by 500ms of phase data which is +30deg or -30deg.
I sample the data at 500KHz, and store to ram to work...
Re: vhdl FIR
Not quite sure, hence posting the code.
intergers are not quite the same as vectors, is the above compiler dependant?
I'm using altium with altera quartus.
the following line is corrected
-- New Sample
sum_int <= conv_integer(signed(t1_DAT_I))* COEF(0);
I realsie that I have...
vhdl FIR
I have the following code for an FIR.
It doesn't seem to be working,
Any comments? Does the principle look ok?
Library IEEE;
Use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;
use IEEE.Std_Logic_signed.all;
entity tim_FIR is port
(
CLK_I : in std_logic...
jtag mosi
There is a switch on the JTAG Adaptor supplied by Altium that switches compatibility between Xilinx and Altera. The adaptor can be used with Altium with full debug capabilities or with the Xilinx or Altera programmers.
The circuit diagrams & functionality of all these parallel port...
altium jtag adapter
These are JTAG cables that connect to a parallel port. They are similar to the parallel port adaptors available from Altera, Lattice or Xilinx, except they have a soft JTAG as well as a hard JTAG. That means they use 4 pins for normal hardware JTAG programming, but the...
vhdl logic_vector
I wish to take a 16-bit logic vector in (from an ADC). This is an AC-biased sine wave connected to an ADC centered around the mid point of the ADC (i.e. 32767).
How do I change this to a signed integer that i then use to do a multiply and subsequently output as a signed...
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