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Hi all~
Thanks for your help for my case. So far I have some concern to attach the schematic of this bandgap. By the way, the resistor ratio is 9.4/2um N+ Poly RPO resistor for each segment, and they are connected in series for higher resistance by inter-digit layout. Right now I am trying to...
The current consumpation is ~159uA, this value is close to my simulation. The bipolar transistor ratio is 16:2, emitter area is 10umX10um wide for each parasitic BJT, and current flow is ~16uA. By the way, if parasitic R and C is the reason, should I extend the test time to see the result again...
The current consumpation is ~159uA, this value is close to my simulation. The bipolar transistor ratio is 16:2, emitter area is 10umX10um wide for each parasitic BJT, and current flow is ~16uA. By the way, if parasitic R and C is the reason, should I extend the test time to see the result again...
Hi~
gate leakage current is antoher concern in choosing MOSCAP as decoupling capacitor. IO MOSCAP can provide smaller leakage current , but you will pay more area to complete the specific capacitance, CORE MOSCAP has opposite relationship. It is due to the gate oxide thickness. MiM has very...
differential pair op amp
Thanks~ The negative and positive input paris are my reference nodes, the reason to do this is to see if voltage level is correct or not. The output voltage of bandgap looks correctly, but those reference nodes make me confused! If N input variation was introduced by...
mismatched differential resistor pair
Hi~
Can anybody help me this? In my bandgap refernce design, the OPAMP was used to force 2 nodes in identical voltage level. However, in my silicon data, the negative input has ~100mV deviation measured from whole wafer (>100ea dice), but positive input...
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