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Recent content by koce

  1. K

    Problem with jtag cable for xilinx cpld

    jtag xilinx cpld open drain Hi everybody, I want to report you that I achieved to make my JTAG cable for Xilinx cpld. Thank you everybody for yours efforts to help me! We should colaborate, shouldn't we!? :o) Bojan
  2. K

    Solution to delaying the signal in VHDL code

    how to delay the signal? Thank you very much to all of you for your efforts to help me. You are all so kind!!! I'll try to delay the signal on hardware way usin the shift registers! :o) Bojan
  3. K

    Solution to delaying the signal in VHDL code

    how to delay the signal? Hi everyone, I use Altera MAXII CPLD for my project. I program it using Quartus II software and VHDL language. With CPLD I control switches using one global clock signal. For one switch, I want to turn it on not on the rising edge of the global clock but to delay the...
  4. K

    Problem with jtag cable for xilinx cpld

    xilinx cpld jtag Hi everyone, I want to download my design on xilinx XC9572-15PCG44 using JTAG cable and xilinx ISE software v_9.2i. The problem is that I can't read ID Code from device. Error is: "The idcode from the device does not match the idcode in the bsdl file" read idcode is...
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