Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by knjr

  1. K

    explanation of VHDL Coding

    Ok. Thanks :) Do you have any idea on how to explain on why I use XOR gate instead of others gates for the c.
  2. K

    explanation of VHDL Coding

    Hi, I got question. [code] C(0) <= NOT c(0); Carry(0) := c(0); C(1) <= c(1) XOR carry (0) Carry(1) := c(1) AND c(0) If I were to keep contiune process. I would need to run again and again. I got mix up. The coding start with 00 00 01 10 11 I should get this result I try to work it out but...
  3. K

    explanation of VHDL Coding

    Hi, I know what does XOR and AND means. I know how it works. Just that I don't know how it get to jump from 00000001 to 00000010 to 00000011. When I work out the coding, I only could get 00000001. 00000010
  4. K

    explanation of VHDL Coding

    c(0) <= not c(0); carry(0) := c(0); c(1) <= c(1) xor carry(0); carry(1) := c(1) and carry(0); c(2)<= c(2) xor carry(1); carry(2) := c(2) and carry(1); Hi, I could get the waveform from 00000000, 00000001, 000000010, 00000011. But I don't understand how it get...
  5. K

    I need a simple ASIC design flow

    Ok. Thank you! :D
  6. K

    I need a simple ASIC design flow

    Do you have diagram of each stages? I got this **broken link removed** Can this be represent as my flow chart?
  7. K

    I need a simple ASIC design flow

    Hi, anyone know any website or know any flow chart of ASIC design flow start with RTL and end with GDS? It's urgent. I need a flow chart with explanation & examples or diagram to guide me. Thanks.
  8. K

    explanation of VHDL Coding

    Alright, I will give it a try. Because I got no time to read a book of vhdl book as my assignment soon need to be hand in. Thanks anyway:)
  9. K

    explanation of VHDL Coding

    Hi, I try to read but it seem like I can't understand it clearly. Can roughly what does each lines does?
  10. K

    ASIC Desgin Flow Chart - RTL to GDS

    I do not need to do with coding. I just need to do research on ASIC design flow chart with examples and diagram so that it would be easier for me do understand it.
  11. K

    ASIC Desgin Flow Chart - RTL to GDS

    Hi, anyone can actually tell me where can I find information on ASIC design Flow Chart starting with RTL and end with GDS? I just need a simple one to help me understand more.
  12. K

    explanation of VHDL Coding

    Hi, I understand the coding for the +1. Now i don't understand the part that is What does each line tells? c(0) <= not c(0); carry(0) := c(0); c(1)<= c(1) xor carry(0); carry(1) := c(1) and carry(0); c(2)<= c(2) xor carry(1); carry(2) := c(2) and carry(1); c(3)<= c(3) xor carry(2); // this...
  13. K

    explanation of VHDL Coding

    Sorry, is it possible to explain from the top onwards?
  14. K

    explanation of VHDL Coding

    library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity my_counter5 is port(count: Out std_logic_vector(7 downto 0); clk: in std_logic; reset: in std_logic); end my_counter5; architecture behav_my_counter5 of my_counter5 is signal c ...
See more

Part and Inventory Search

Back
Top