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Re: contact redundancy
What margin do you mean? MT enclosure? Or MT to via surrounding MT spacing? Or both?
I've a situation that there's no room to add second via beside exiting one unless if you extended metals (via spacing + via enc + mt spacing rules should be met all)..
Although via's...
Gents-
I have a BIG design with so many single vias.. I had a script that adds redundant vias when possible such that add vias doesn't violate DRC (MT spacing and ENC)
Nevertheless, there're regions that couldn't be fixed, surrounded by a close metal lines (Mx, Mx+1 or both) that is followed...
Hi,
Anybody experienced in BE verification can help me regarding how to link Calibre LVS to Assura QRC? What are the documents talking about that point in particular?
I have slight information about CCI output from Calibre LVS which is a format that is somehow fed to QRC. But I need some extra...
Hi all,
I wonder if one of you have a simple way to capture neat figures from Cadence simulation results (AWD waveform tool) ??
Also, regarding schematic capture, how can un-display all data of MOS transistors unless W and L? Or in general, how can i hide unwanted parameter from component on...
drc poly density
Hi,
What's the best way to correct "Density" errors got from running DRC on certain layout?
What let them come originally? i.e. What's their important in reality??
Thanks,
Cheers,
--Knack
Hi there,
I have a question that i think basic; in VHDL-AMS what's the difference between TERMINAL, PORT, and SIGNAL assignment?
When should I use ELECTRICAL attribute and when should I use INOUT and so on?
This confuses me a lot!!!
Say what, can anybody give me a quick tutorial or reference...
FThank you all,
But it seems that you still didn't get what i want to know..
From your replies, if i don't know, i may go to use a 1µF on Chip cap and 1MΩ resistor!!!!!!!!!!
I want numeric typical values :D
Thanks
Cheers,
-- Knack
Hi hadi20 :)
Thank you for your nice prompt reply :)
Do you have some books/papers regarding VCO robus design for the selected range?
Another thing, regarding VCO biasing, we're a team of 7 undergraduates, on of us will take biasing of other blocks... what does this mean? will that guy provide...
Hi,
In design of a complete PLL on chip using 130nm technology, what's the maximum/minum allowed values of on-chip resistors, capacitors, and inductors (R,C, and L)..
Also, is there some tricky ways to override these values (e.g. MOS resistor and capacitor rather than poly R and MIM cap...
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