Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I am designing a regulated charge pump.
I want to supply vdd of this circuit using output voltage.
But in output stage, parallel value of all transistors' "on resistance" can be a load.
So the load value is too low, charge pump can not operate.
How can I solve this problem? :cry:
hi
do you know how to design the comparator has higher reference voltage than vdd?
this is my spec:
vdd : 0.8v
reference voltage : 1.3v
input range : 0 ~ 2.5v
is it possible?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.