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Yes, I mean when I simulate before the synthesis circuit works correctly. Also when I try to <report_clocks> from the top level it gives the name of the clock that I've created before, but when I write in dc_shell:
<current_design 'mySubModule'>
<report_clock>
it says that no clock is present
Hi Everyone,
I'm trying to synthetize my circuit composed by several submodules and I've created a clock using <create_clock -name "CLK" -period 5 CLK> in my very top level, but when i go inside a submodule and go to check the clock there the shell says that the current design has no clock...
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