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my design only has 2 outputs(uart clock and uart data), everything else is supposed to be internal.
thanks, but aren't constraints more for optimization? either way I reading lattice's Lattice Diamond Tutorial and Lattice Synthesis Engine for
Diamond User Guide
I`m looking at the reports generated by diamond and I found this in latice LSE: top,
WARNING - synthesis: c:/users/daniel/desktop/projects/fpga/lattice/rs232/main.vhd(14): using initial value "1010101101111100" for s_tx_data since it is never assigned. VHDL-1303
WARNING - synthesis...
it an off the shelf fpga
I'll try to find this constraint file, but I have no idea where diamond keeps it, i looked at some of the timing analysis view tool but I dont think thats it. out of curiosity is it the spreadsheet view?
From the netlist Analyzer that diamond generates, I believe that it is (all but the port P_STDBY of UART.vhd, it is declared but it isn't being used in the code)
I don't know how to check that. The only resource the I actually used to learn how to use a fpga is the book Free Range VHDL, so...
sorry for taking so long. you were right, I had forgotten that my logic analyzer isn't fast enough for this task. I checked the 10 MHz UART clock with an Oscilloscope and the clock seems to be stable at 10 Mhz, the value it is supposed to be.
The Uart portion however is not outputting anything...
update, I put a simple clock divider written in vhdl and the clock signal is mostly at 125kHz, with sometimes with a one 10us pulse. I'm going to look at the signal generated by the internal oscillator and see how it is behaving (the logic analyzer i have isn't fast enough for 113MHz)
Hi, I'm trying to write a simple program for sending data from the fpga to a computer through a usb to rs232 converter, Ftdi Ft232rl. I want to send 2 bytes of data then '\r\n'. I am using a lattice MachXO3L-6900C FPGA and simulating with Active-HDL lattice edition. Also I am new to FPGAs so I...
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