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Recent content by kishornakul

  1. K

    What is a chip rate and simbol rate?

    Bit is a fundamental information unit to be transmitted But symbol is a unit of transmission energy, sinusoidal or wave transform. bit rate = k*symbol rate= k/T where T is a symbol duration
  2. K

    RTL design TOOL ideas

    Hi friends, Good afternoon to all, I am new to RTL design. Anyone know about what are the RTL tools used in Wipro, HCL for IC design.
  3. K

    [moved] How to setting up environment for design compiler

    Re:How to setting up environment for design compiler If you installed a software, that need for setting up the environment. Follow the steps: my computer->system properties->advanced->Environment variables click->new. Here itself you have to give license name and its location
  4. K

    carry increment adder error in VHDL

    Re:carry increment adder error in VHDL When you access a VHDL library, the library must be declared and then used as follows: library <my_lib>; use <my_lib>.<my_pkg>.all; If the package name listed in the usage line does not match a package name in the library file, this error results. Be...
  5. K

    [SOLVED] Verilog waveform question (using online simulation website edaplayfround)

    Re:Verilog waveform question I did simulation using your testbench code itself and also it runs after 15 time units also in Modelsim 6.3c. Set tour run length as 5 time units.
  6. K

    Physical design idea needs

    I am new to vlsi physical design but i need to join a job related physical design. So what are the materials should i refer?
  7. K

    file handling in verilog

    I need to know, how to write a constant value in file handling process. In my project, i am doing image processing using vlsi. I got a text file in binary format using image to text. In text file, i am getting "1011" means for the value "1" i am replacing "1100" or value "0" means "0011".
  8. K

    Steps to convert MATLAB code to HDL or VHDL

    Re: MATLAB to HDL converter Yes it is possible. Before that you have to install vivado system design. By using xilinx system generator you can convert simulink model into HDL
  9. K

    doubt in 3dB level calculation

    Re: doubt in 3dB level calculation 1) 3dB value is taken only for the purpose of original Bandwidth calculation. 2) 0.707 value represents RMS(Root Mean Square) which is the value of 1/square root of two
  10. K

    stepper motor vhdl codes

    Re: stepper motor vhdl codes Check your clkdiv.vhd code. There is port mismatch, it means "clkdiv.vhd has 2 input,2 output but in driver.vhd component declaration only 2 input and one output. Then mclk and clr is not declared anywhere in driver.vhd so check it Did you find this post helpful...
  11. K

    FPGA with build-in flash

    Re: FPGA with build-in flash Hi, Each and Every FPGA kit can able to program using Read Only Memory. So use ROM memory.
  12. K

    how to calculate delay in Tanner EDA v14.1

    Hi friends, I draw some circuits using those circuit schematic. But I know how to calculate propagation delay of the circuit???. If anyone know the answer, please tell me briefly.
  13. K

    [Moved] Procedure for Xilinx System Generator

    Hi friends, I know something about xilinx system generator. But the problem is "i don't know how to use it" and By using system generator whether the circuit convert into HDL or not.
  14. K

    VLSI Physical design

    Hi friends, i want to know about VLSI physical design concepts, i am new to this. So please help me to share the links about VLSI physical design and explain me about it.
  15. K

    Procedure for h-spice

    Hi good afternoon to all, I am having hspice_vA-2008.03. i don't know how to use the tool. Anyone know about h-spice and what are the designs able to do using h-spice and also tell me the procedure.

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