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Hi all. Thanks in advance. I don't know what happened to my spice netlist out, the bus notation was __ but not <>. For example, _6_, _5_,... but not <6>, <5>....Could someone let me know how to reset it and back to original <> notation? In which setting file can I switch it back?
Thanks a lot.
Hi, all,
I am simulating in Cadence ADE with spectre. I use a VPWLF source to get a pwl external file as a stimula. In my spectre bench, I have set some variables(Fosc, vdd, for example). I compose the pwl file with these variables in math operations to define the pwl waveform. But when spectre...
Hi, all,
I am simulating in Cadence ADE with spectre. I use a VPWLF source to get a pwl external file as a stimula. In my spectre bench, I have set some variables(Fosc, vdd, for example). I compose the pwl file with these variables in math operations to define the pwl waveform. But when spectre...
Hi All,
Is there any one familiar with USB2.0 and BC1.2 spec.?
Device connection detection requires device to pull up 1.5K Ohms resistor, but won't this conflict with BC1.2 charger type handshake electrical characteristics?
BC1.2 requires PD to force a 0.6V at DP when doing handshaking. But the...
Hi Pjdd,
Thanks for your help.
I have no schematics, it's the requirement to meet.
I only have the idea but no solid circuit that's why I post it to ask help.
Thanks.
Hi...
I am doing a project and needs a circuit with/without Opamp to produce a 4X voltage drop from a voltage drop.
Can anyone help me to find it out?
Thank you very much!
Something like below or else.
The start-up voltage at VBG is 2*VD-VBE. This voltage at VBG will give current to left NPN, hence right NPN.
After loops, the VBG should be steady at around 1.23V.
What I think is in any condition, even there is zero current through BJTs, the VBG should be larger than VBE, why there
are dies...
Will the transient simulation show the real chip behavior of bandgap including start-up circuit? I mean if the model was correctly characterized.
What will be other factor to let bangdap fail when wafer is out if WAT data is OK?
Will the transient simulation show the real chip behavior of bandgap including start-up circuit? I mean if the model was correctly characterized.
What will be other factor to let bangdap fail when wafer is out if WAT data is OK?
Hi all,
My bandgap circuit is as attached. With a start-up circuit using long channel length PMOS as resistive load and 2 diodes in series.
Now my wafers show low yield in VBG. Good dies show good distribution, but bad dies are all 0V.
Can anyone help me to figure out low yield is due to...
Hi Tony,
Thanks for your help.
But there is another issue. Since there is also a constraint that the comparison delay time should be limited within a short period. If we do in this way,
will the comparison delay time be increased a lot?
Thanks for your reply.
---------- Post added at 03:02...
Hi all,
I am doing a comparator with conditional offset. It needs the offset should be about 30mV when compared level is about 0V; and offset should be < 5mV when compared level is > 0V and < 2V.
The supply is 5V. I was thinking is there any way to activate an optional input gate or to activate...
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