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Recent content by KICHA14

  1. K

    What is the Logical pin in top level

    Logical Pin is a hierarchical Pin which is defined at each module entry/exit. This logical pin will become physical pin once you start doing the pin placement in the Place & Route Tool. After Floorplan, next thing will be your Pin placement. By doing so, you will place the logical pins on either...
  2. K

    How to do MMMC Analysis In Cadence Encounter?

    Plz check for EDI User guide in Cadence Support website There many settings to be set for MMMC analysis, guide would be better for detail explanation
  3. K

    adding filler cells in soc encounter

    ENDCAP/DECAP/FILLER: - Endcap is used at the boundary b/w two independent physical blocks. Like end of rows; around the macros. There different types of endcap cells for top, bottom, left, right & for corner. - De-cap cells are used to provide extra cap to the nearby logic cells. It helps in...
  4. K

    how to select wire load model for synthesis

    Refer this link for explanation on wireload selection. https://asic-soc.blogspot.in/2013/07/wire-load-models-for-synthesis.html
  5. K

    Removing set up and hold violaions at RTL level

    Yes, you can completely ignore hold at RTL coding level, as it is completely related to skew and balancing the clocks.
  6. K

    Synthesis : who we finalize synthesis, which report should we check and clean?

    In General, if TIMING is MET for your targeted frequency, you are good to start with PnR. But you should also check the above points posted by "slutarius" and make sure you are OK with Area; FF count; Power; etc.

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