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Thanks erikl. I thought it might be something like that, but on the one hand I thought 3% is quite large, when there is another conductor below it and enclosing it, and on the other hand, as I said, the Assura documentation doesn't talk about fringe capacitances, but only about overlap (i.e...
Havent tried to install on Ubuntu, but are your paths configured correctly?
You don't seem to have a symbolic link from /tools to /tools.lnx86, as is commonly the case.
Hi,
I have a question regarding parasitics in PIP capacitors.
I am trying to extract parasitics from a single PIP capacitor in the AMS 0.35um technology.
For a 100fF capacitor (approx. 10x10 um) Assura gives me 25fF bottom plate parasitic, which agrees with the process parameters.
However, it...
Are you sure you are simulating the right thing? It looks like the OSC input is an enable signal. When OSC=0 then the NOR gates on the left work as inverters. Hence you have a six-inverter ring-oscillator where you take outputs from the 3rd and the 6th inverter. The gates on the right then...
Re: calibre PEX errors
The first errors are clear. Check why the respective terminals are missing in the schematic.
Also, there is an option during PEX or calibre view creation that allows you to create all terminals, that is even if they are missing in the schematic.
However, I would be...
Yes you can. As long as you are referring everything to the same ground.
All you have in a circuit is voltage differences. You can operate the same circuit with 2V and 0V(GND) or 1V and -1V. If in the first case the circut can have an output from 200mV to 1.8V, then in the latter case the same...
- The input impedance of the integrator (which is R2) effectively comes in parallel to the LPF capacitor, forming a voltage divider. This is the reason that your signal at node004 is much smaller than your input signal (effectively by R2/(R1+R2)).
- The signal at node n001 SHOULD be almost zero...
It is reasonable that you get different results with the second loop open or not, as you simulate a different system in the two cases! When you break a loop, you calculate the open loop transfer function for this particular loop. Then you use this open loop gain to estimate phase and gain...
LvW is right in all his points. Just to try to make it a bit more clearer, if there is no DC path in the feedback, then any DC signal at the input, no matter how small (offsets etc) will charge your capacitor, leading finally the opamp to saturation and the output to the rail.
Also, when you...
Re: Bandwidth of OPAMP
If you place the opamp in a closed loop, as is almost always the case, it depends on the feedback. The gain-bandwidth product (=UGB) is constant in a voltage amplifier, so the lower the gain of the feedback path (return ratio) the higher the closed loop dominant pole in...
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