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library characterization
Hi All ,
I have the skill to help you characterization timing of standard cell , Memory , ROM, IP...special circuit to be timing library(.lib) and function library (.v).
If you are interested at this buniness, you can contact me. thanks
I have many case of different...
In the future, the timing model of Astro (IC compiler) will be the same as PrimeTime.
Synopsys will release IC compiler in June. It include PrimTime as timing engine and Star-RCXT as RC engine....
verilogxl+sdf
Normally , the sdf version is v2.1.
In your case , you shold to check the SDPD ( state depend path delay)whether are the same between Verilog and Synopsys or not .
:o
sdf file format synopsys
Hi ,
(1)
(IOPATH (posedge S0) Y (0.179:0.290:0.290) (0.156:0.253:0.253))
(IOPATH (negedge S0) Y (0.164:0.265:0.265) (0.144:0.233:0.233))
This Error messge is indicated that the IO path are different between Synopsys and Verilog model.
You should check the IO path...
Hi ,,
LSF is not a freeware. You must pay the money to use it.
You can have alternative choice. SunGrid is the best software.
It is free and powerful. SunGrid have the Solaris and Linux version.
You can download the free version on the Sun website.
Check it ~
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