Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello,
I have a question that maybe someone can answer me:
Does anyone have experienced a bit inversion in a serial line, always in a fixed position of the message, due to a bad startup of the FPGA? We have a hardcode in the FPGA (the address of the unit, that is hardcoded in the FPGA pins)...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.