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Hello there,
I'm trying to make a testbench in SystemC for a VHDL DUT.
My question is how can i access internal signals from VHDL using the SystemC?
Modelsim has macros like $init_signal_spy, $signal_force ....
Is there something like this macros for cadence tools? Is there other methodology...
My doubt is about the communication between modules using events on systemc language.
In the book SystemC: from the Ground up there is a chapter named The interrupt, a custom Primitive Channel, with the sample code below that do that...
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