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you can reduce the res R121 and R214 to let down bias point of Q1, set Q1 on less Quiescent Current point,you will get larger amplitude for your OSC. simultaneously, increase cap C111 to maintain (R121||R214)*C111 constant!
Re: integrator
Did you use cadence's idle “opAmp”? what is you input signal?and how long the integrated time? I think you can reduce you input signal or integrated time, orther way,you can clamp the idle "opAmp" output swing (eg:0~5V).
Best regards!
I see,you have not enough voltage swing.then in the instance you just let it work in the weak inversion region,as I know there would be no problem in the application.
So your transistor M1 works in weak inversion region,don't care! But I would recommend you to scale down the transistor M1 and M2. Made the transistor size large,did you mean that you care about the noise?
diffusion resistor
I agree the point lianggu said. poly resistor is more easy to be demolished by the ESD thermal. We know a ESD device must protect itself from ESD current first,and then it can protects others more.By the way,N-well resistor welcomed in ESD.
I also agree that your transistor just working in the weak inversion region,maybe the dimension was too large.then 20uA current Ids is. By the way, you say that the ckt is just a simple current mirror,whether 20uA just mirrored the Iref current?
double ramp adc schematics -patent
You can refer to the datasheet such as ICL7106,TC7106.Easily found by google.
By the way,in the market,Integrating ADCs are almost based on HV Process,Why?If there any application restricted?
* process : 0.35um mixed mode
Hi, does anyone have used TSMC 0.35um MIXED MODE Process? It seems the noise is large while comparing with other 0.35um MIXED MODE Process.
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