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Hi All,
I am having a EBD model of DIMM. I want to simulate it in virtuoso environment with spectre simulator. I didn't find any options to include EBD file. So How can it be simulated with spectre?
Thanks
Re: Damping Freq of Oscillation cadence
It is a simple passive series RLC circuit.
Ok let me be clear about this.
Damped Frequency is the frequency at which an underdamped system oscillates when excited. It is denoted as Omega_d
There is a relation between Undamped frequency (or...
Re: Damping Freq of Oscillation cadence
That's none of your concern. I used it to mention I am simulating it using cadence virtuoso ADE L. Yeah, I used wrong terminology and will correct it hereafter. You have the right to say "use correct terminology". But asking "Are you a Cadence's...
Re: Damping Freq of Oscillation cadence
We are talking about series RLC cicruit.
It wont change the resonant frequency as long as the energy lost in each cycle is compensated.
And it does change with damping ratio. And for underdamped system.. this is called as damping...
Re: Damping Freq of Oscillation cadence
So if the system is non linear then there is no specific damping frequency right? The oscillations start at natural frequency and the frequency decreases gradually as the oscillations die out. Am I
right?
RE: Damping Freq of Oscillation cadence
Hi All,
I have simulated a ideal LC oscillator without damping in cadence with L= 2nH and C=1pF. The natural frequency of oscillation is Fn = 3.56G.
Now I have added a damping resistor value of 10 Ohm and still the output is oscillating...
RE: Electromigration simulation SEB flow
Hi All,
Heard about SEB(Statistical EM Budgeting) flow to measure FIT(Fails in Time) for interconnects. It includes joule heating of inter connects as well as self-heating. Anyone know how to do this in spectre...
Hi,
See, If you know something.. please share it politely.
. Can or cannot depends on myself only, So never say like this.
Coming to the point, We do this to measure the differential loss in my side and I know about the mode conversion and it needs more than 2 ports. In my design I...
Hi,
I have gone through the attached threads. It is similar to this question but, in the attached snap there is only one port so S11 only available. And I assume this as return loss. In that case I assume Z0= 100 Ohms(Port Impedence).
so how to calculate Z1 so that i can substitute...
Hi,
In cadence S11's magnitude is 299.717m , I assumed 1V(for understanding), so that I said it is 299.717mV. Anyway I correct this. This doesn't mean I should review my knowledge. Before commenting like this, you should understand what other person is trying to say. Watch your...
Hi All,
I was doing S-parameter simulation in cadence to find out the differential loss of a simple circuit. I know the simple formula for return loss Return Loss = (ZL-ZS)/(ZL+ZS).
For simple resistor circuits the hand calculation and the cadence simulation results are same. For the...
Re: via spacing in Layout
Hi all,
I think this post has the answer for my question. https://www.edaboard.com/threads/95934/
In this post, They say large Via cause more stress so we split vias as small holes. Is that right?
Thanks
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