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Inductance is often a limiting factor so high voltages are used to reduce the rise time with a fixed inductance. 5nH is typical of the package inductances. If you want a very fast rise time/short pulse, the only way is with a high voltage if you are stuck with such an inductance. The high...
I am not a big user of I2C but as shown in the graph from andre_teprom it is highly dependent on the capacitance. Assuming the components in the original post are on the same PCB I doubt that the pullup resistor is the cause of the erratic results (unless the pullup being used is 100k ohms or...
If you slow down the timebase the sampling rate will change. Usually this is shown on the display somewhere. There are ways of avoiding this depending on the oscilloscope. I always run mine in 'envelope' mode where it samples at the maximum rate and then takes the max & min values in a certain...
If you are using a digital sampling oscilloscope it sounds like you are looking at aliasing of the high frequency signal with the oscilloscope sampling frequency. The 20Hz is the difference between your clock and the sampling clock (or a multiple)
Keith
Unless it supports BSIM 3 and BSIM 4 models then it will be no use for IC design. Also, netlist export for LVS is a requirement as is AC analysis.
LTspice is workable for bipolar IC design I believe but I don't think it includes the necessary BSIM models for CMOS IC design.
Keith
You final output stage looks suspect. How much quiescent current is there in the final stage? A fixed voltage to the gate of the transistor is a poor way of doing things even for a proof of principle. A current source or current mirror would be better.
Keith
Re: ekspansi memory 4kx8 to 256kx8
My guess is he want a circuit to expand 4kx8 memory to 256kx8 but this is in the FPGA section so may need moving.
Keith
I don't think Falstad will be much use doing IC design. As Dick suggested, LASI is probably one of the few (only?) free ones. I have used it for layout but I must admit to using a commercial Spice package for simulation.
Keith
Same thing - programmed by metal at the end. The difference is the structure of a gate array is a simple, repetitive "sea of gates" whereas a structured ASIC can have a more complex structure.
https://en.wikipedia.org/wiki/Structured_ASIC_platform
Keith
With gate arrays the processing is stopped before final metal layers and the wafers stored. The final metal layers are added later to suit the customers requirements.
Keith
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