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Recent content by keeth

  1. K

    Verilog Conditional assign statements

    Yeah. I did follow the syntax. I m generating a set of 75 values in a module and i m trying to pass it to another module where the conditional assignments are needed. this is a piece of my code. always...
  2. K

    Verilog Conditional assign statements

    Hi.. Can we use multiple assign statements for a single condition? for example case(condition) begin a1=b1; a2=b2; a3=b3; end i...
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